This invention relates to a data processing system, and more particularly to a data processing system which is constructed, by using no private circuits group but using low-speed logical circuit elements, into a structure suitable for conversion into an integrated circuit, thereby to effect the data transfer between a high-speed input/output unit and a central processing unit (CPU), or to effect various types of data processings at high speed.
Generally, demanded of a data processor are the functions including the "serial" to "parallel" conversion, buffering, and error check (cyclic redundancy check), of input/output data, the detection on judgement of the peculiar marks (discrimination Nos.) labellled to input/output data format, the generation or production thereof, the data link between the system and the CPU, etc.
In order to achieve these functions, a conventional data processor is formed into two types of hardware structure, one of which is a random logic type provided with a private-circuits group for executing the above-mentioned functions, and the other of which is a matrix type provided with a general-circuits group for performing the above-mentioned functions. In the case of the random logic type, a private circuit is exclusively used for each function. The hardware structure of the random logic type is not effective to convert into an integrated circuit but, even if the operation processing speed is low, it will not cause any inconvenience to such a data processor. In the case of the matrix type, the data processor is formed mainly of a working-registers group, a Read Only Memory (ROM) and a Random Access Memory (RAM), and its operation is executed in accordance with the instructions read out from the ROM for each prescribed machine cycle. Here "machine cycle" means the intervals at which the instructions are read out from the ROM one after another. Thus, during the machine cycle each instruction from the ROM is executed. Usually, each instruction is executed within a time shorter than the machine cycle, and no instruction is executed during a portion of the machine cycle. In this case, the circuits in the processor are arranged in the form of a matrix and therefore easy to convert into an integrated circuit. Since, however, each of them is generally used, the processor should carry out its operation processing at high speed. In the case of the matrix type, however, it is necessary, for this purpose, to provide a private-circuits group (increase the random characteristics). Further, upon integration of this matrix type data-processor on one chip, the following problem will arise.
Namely, in the case where a higher level of an operation functions are incorporated, they should be so done with high density. Simultaneously, in the case where they are realized with the Large Scaled Integration, an integrated circuit technique for use in a MOS (Metal Oxide Semiconductor transistor) structure has to be used. The processing speed of the MOS transistor circuit, however, is generally lower, to an extent of one or two digits, than that of a bipolar transistor circuit. Accordingly, in order to convert the matrix type processor into an integrated circuit by the use of the MOS structure and permit it to carry out the high speed processing operation, consideration must be given to a circuit architecture of the processor.
It is considered that this architecture includes the following two methods.